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Copper has drawn much attention as the
next generation material for the
interconnect lines of silicon chips, owing
to its excellent conductivity and high
electromigration resistance. The primary
choice for the deposition of copper
interconnect lines is
electroplating, because this
method enables a high deposition rate and
the capability of
“deep-filling” substrate
features with high aspect ratio. Owing to
the rapid diffusion of copper in silicon,
of course, a diffusion barrier layer of TiN
or TaN must be deposited on the silicon
surface prior to the deposition of copper.
Electroplating of copper onto the surface
of an insulator requires a seed
layer, which serves as a conductor for
the plating current, and the structural
quality of the electroplated copper lines
critically depends on the uniformity of
this seed layer. Typically, the seed layer
is made by sputtering and consists of
individual nanoscopic copper clusters.
In this project, we study the formation
mechanism of plating defects,
which often arise in electroplated
interconnect lines because the copper
clusters in the seed layer
agglomerate. For this purpose, we
analyze the structure, morphology, and
spatial distribution of copper clusters
deposited under various different
conditions and investigate the formation of
plating defects in early stages of copper
electrodeposition. An important tool for
this study is transmission electron
microscopy.
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